The repetoire of digital computers commonly contains a count ones instruction, which instruction computes the number of bits in a data word which are equal to binary "1". This computer count ones instruction may be implemented either under discrete logical or microprogrammable control. The generalized prior art computer logical structure for the implementation of a computer count ones instruction is shown in FIG. 1. The count ones instruction is typically implemented by shifting the data word as resides in DATA REGISTER 102 one bit at a time. The shifted-off bits are captured as represented by block C 104 and then added together, one at a time, by inserting them as the carry of an add operation performed within ALU 106. The intermediary sum is held in RESULT REGISTER 108. At the conclusion of the shifting and adding together of all bits, RESULT REGISTER 108 contains the final number of ones which were within the original data word.
The prior art method of performing the count ones instruction requires a shift and an add for each bit in the data word. Special hardware can combine the shift operation and the add operation into a single computer clock cycle in order to give a net instruction execution rate of one clock cycle per data word bit. If the embodiment of the shift operation and the add operation was enabled under microprogram control, one micro instruction execution time would be required for each bit within the data word. For example, a data word of 32 bits would require a minimum of 32 clock cycles, or microinstruction times, for execution of the computer count ones macroinstruction.